Field of the Invention
The present invention relates to a semiconductor memory device such as a NAND-type flash memory, and in particular to a data setting method for setting data input in synchronization with an external clock.
Description of the Related Art
A NAND-type flash memory reads data and programs page-by-page, and the page data is stored in a page buffer. The flash memory disclosed in Patent Document 1 includes a first mode in which data stored in the page buffer is transmitted in a first bit width and a second mode in which data stored in the page buffer is transmitted in a second bit width, and a plurality of operation modes are provided.
Patent Document 1: JP2012-253591
FIG. 1 shows a configuration example of a part of a NAND-type flash memory. A page buffer 10 holds the page data read from a memory array (not shown) and holds the page data to be programmed into the memory array. A column selection circuit 30 is connected to the page buffer 10 through bidirectional digital lines DL/DLb20. During a read operation, the column selection circuit 30 outputs the selected data from the page buffer 10 to a data bus 40 in accordance with the column address. During the programming operation, the column selection circuit 30 sets the data to be programmed according to a column address to the column selected by the page buffer 10. The column address is input by an external terminal input or generated by an address counter built in the column selection circuit 30. An input/output circuit 50 is connected to an m-bit external input/output terminal 60 (m is an integer of 1 or more). During a read operation, the input/output circuit 50 outputs the data of the data bus 40 to the external input/output terminal 60. During a programming operation, the input/output circuit 50 outputs the input data from the external input/output terminal 60 to the data bus 40. Assuming that the bit width of the data bus 40 is greater than m, the input/output circuit 50 takes out the read data from the data bus 40 a plurality of times, or loads the input data into the data bus 40 a plurality of times.
The NAND-type flash memory has an ONFi type that uses an external control signal (address latch enable signal, command latch enable signal) for address or command input. The NAND-type flash memory also has a Serial Peripheral Interface (SPI) type that does not utilize this external control signal but synchronizes the serial clock signal from the outside to input data, addresses, and commands. The SPI type has a small number of terminals and can be miniaturized and reduce the cost.
FIG. 2 is a block diagram showing the details of the column selection circuit of FIG. 1. Here, in the flash memory equipped with the SPI function, the operation at the time of sequential setting the input data (to be programmed data) of the input page buffer 10 during the programming operation will be described.
A timing control circuit 80 receives a write trigger signal W_TRG, and outputs a write clock signal W_CLK to a logic circuit 86 in response to the write trigger signal W_TRG. A delay circuit 82 receives the write clock signal W_CLK output from the timing control circuit 80 and generates an internal clock signal I_CLK delayed by a predetermined time Td. A column decoder (YDEC) 88 responds to the internal clock signal I_CLK, receives a column address CA generated by an address counter 84, and outputs a column selection signal YS obtained by decoding the column address CA to the page buffer 10. The address counter 84 increases the column address CA in response to, for example, the falling edge of the internal clock signal I_CLK. The updated column address CA is output to the column decoder 88 and the logic circuit 86. The logic circuit 86 selects the digit lines DL/DLb20 according to the column address CA generated by the address counter 84 and writes the data of the data bus 40 into the selected digit lines DL/DLb20 in response to the write clock signal W_CLK.
Next, the operation of the timing chart of FIG. 3 will be described. The write trigger signal W_TRG is a signal synchronized with a clock signal CLK supplied from the outside. When receiving the write trigger signal W_TRG at a time point t1, the timing control circuit 80 outputs the write clock signal W_CLK to the timing logic circuit 86 at almost the same time. The logic circuit 86 selects the digit lines DL/DLb20 based on the column address CA generated by the address counter 86 and outputs the data of the data bus 40 to the selected digit lines DL/DLb20 in response to, for example, a rising edge of the write clock signal W_CLK. Although not shown here, the logic circuit 86 includes a write amplifier, and the write amplifier outputs the differential data to the digit lines DL/DLb20.
The plurality of digit lines DL/DLb20 are each connected to latch circuits of corresponding columns of the page buffer 10 through a plurality of column select transistors. For example, when the page buffer is a 2K byte, if the number of digit lines DL/DLb20 is 16, a pair of the digit lines DL/DLb20 is connected to latch circuits of 128 columns. If the number of digit lines DL/DLb20 is 32, a pair of digital lines DL/DLb20 is connected to latch circuits of 64 columns. The plurality of column select transistors are selectively opened and closed by the column select signal YS. When the column select transistor is turned on, the corresponding latch circuits of the page buffer 10 are electrically connected to the digit lines DL/DLb20. Since the physical wiring of the digit lines DL/DLb20 are connected to the plurality of latch circuits as described above, the wiring capacitance and wiring impedance of the digit lines DL/DLb20 are relatively large, and thus it takes a certain amount of time for the driving of the digit lines DL/DLb20 to reach a sufficient level by the write amplification.
The delay circuit 82 sets the delay time Td that is longer than the time required for the write amplifier to drive the digit lines DL/DLb20. As a result, at a time point t2, a column select signal YS which is delayed by a time Td from the write clock signal W_CLK is generated. At the time point t2 when the potential difference of the digit lines DL/DLb20 reaches a sufficient level, the column select transistor is turned on and the differential data is set to the latch circuits of the corresponding columns of the page buffer 10.
Next, at a time point t3, the address counter 84 automatically increases and updates the row address at the falling edge of the internal clock signal I_CLK. Time point t3 indicates the time point at which the data of the digit lines DL/DLb20 is written to the latch circuits of the page buffer 10. The column address updated by the address counter 84 is output to the logic circuit 86 and the column decoder 88, the following input data is set to the page buffer 10, and eventually the data of one page to be programmed is set to the page buffer 10. The programming operation to a selected page is performed.
In the NAND-type flash memory, if the operating frequency of the external clock signal CLK is increased, the next write clock signal may be generated before the increment of the column address, and the wrong data may be set to the latch circuits corresponding to the column address before updating.
FIG. 4 illustrates the problem of the operating frequency of the external clock signal CLK being high. At time point t1, in response to the rising edge of the write clock signal W_CLK, the logic circuit 86 starts writing differential data to the selected digit line DL/DLb20 in accordance with the column address. The writing of the digit line DL/DLb20 requires a certain write time Tw as described above. After a delay time Td that is greater than this write time Tw, the internal clock signal I_CLK is supplied to the address counter 86 and the row decoder 88. At time point t2, in response to, for example, the rising edge of the column selection signal YS, the column select transistor is turned on and the data of the digit lines DL/DLb20 is set to the latch circuits of the corresponding columns of the page buffer 10. At time point t3, the address counter 84 performs increment in response to the falling edge of the column selection signal YS or the internal clock signal I_CLK. However, when the operating frequency of the clock signal CLK becomes high, the frequency of the write trigger signal W_TRG synchronized with the clock signal CLK also increases, and the write clock signal W_CLK is generated at a substantially same time. In this way, as shown in FIG. 4, before the next column address CA is updated, the next write clock signal W_CLK is generated at time point t3′, which violates the timing. As a result, the logic circuit 86 selects the digit lines DL/DLb20 according to the column address before updating and the page buffer 10 selects the column select transistors according to the updated column address. The selected digit lines DL/DLb20 do not match the selected column select transistors, and the input data cannot be correctly set to the paging buffer 10.
On the other hand, although the write time Tw of the digit lines DL/DLb20 is also considered to be shortened, this write time Tw is mainly affected by the RC constant of the digit line DL/DLb20. If it is shortened, it is impossible to avoid the circuit size and area increase.
In order to solve the conventional problems described above, the present invention aims to provide a semiconductor memory device and a method of setting input data capable of correctly setting input data.